1. Field of the Invention
The present invention relates to a process for the manufacturing of a DMOS-technology transistor, particularly a power or non-power DMOS transistor such as a power MOSFET, an IGBT or an MCT, providing for a single thermal process for the formation of source and body regions.
2. Discussion of the Related Art
Conventionally, in DMOS (Double-diffused MOS) transistors the channel region is obtained by exploiting the different diffusivity of the two dopant species used to form the body regions and the source regions, each of which regions is formed by means of different thermal processes.
By way of example, a process for the manufacturing of an N-channel DMOS transistor generally starts from an N+ substrate, over which an N type layer is epitaxially grown. A gate oxide layer is then formed over the N type epitaxial layer, and a polysilicon layer is formed over the gate oxide layer. Gate electrodes are then formed by means of masking and selective etching of the polysilicon and gate oxide layers.
By means of the same mask used to define the gate electrodes, a P type dopant is then implanted, and a subsequent thermal process is performed for diffusing the dopant so as to form the body regions.
In particular, boron is used as the P type dopant for the body regions; as known, boron has a diffusivity sufficiently high to make the body regions diffuse adequately under the respective polysilicon gate electrodes. The diffusion of the body region under the gate electrode define the device's channel length.
A masking is then optionally performed for defining the source regions, and an N type dopant is implanted. The N type dopant is then made to diffuse by means of a subsequent thermal process, so as to form source regions inside the body regions.
N type dopants normally employed are arsenic, phosphorus or antimony, all of which have diffusivities lower than that of boron.
The difference in the diffusivities of the dopants used to form the body regions and the source regions allows forming channel regions of the DMOS transistor under the gate electrodes.
A drawback of the process described, that provides for performing two distinct thermal diffusion processes for the formation of the body regions and the source regions, is the long time needed to form the these regions.
In fact, rapid temperature changes can cause substantial thermal stresses of the silicon wafers, stresses that are greater as the diameter of the wafers increases. Such thermal stresses can cause an increase of the number of defects in the components integrated on the chips of a silicon wafer. Thus, the steady-state temperature of the diffusion processes must be reached quite smoothly.
Similarly, at the end of the thermal process the temperature must be lowered quite slowly. Typically, the steady-state temperature to be reached for thermally diffusing the above mentioned dopants ranges from 1000 and 1150.degree. C., and the diffusion times varies from 1 to 10 hours. This times, already quite long, must thus be added with the time necessary for gradually rising and lowering the temperature of the wafers.
Additionally, it is known that when the thermal diffusion processes are performed in ovens, in order to have stable and reproducible thermal diffusion processes the diffusion times cannot be too short. Thus, it is not possible to excessively reduce that part if the thermal process performed at the steady-state temperature.
For all these reasons, it is not possible to decrease the size of the devices so as to achieve a higher cell integration density without impacting the device performance.
These constraints impose a lower limit to the time necessary for the manufacturing of the devices.
Another drawback inherent to the formation of the body regions and the source regions by means of two distinct thermal processes is the photolithographic misalignment, that makes the channel length difficult to be controlled.